1. Field of the Invention
The present invention relates to a prober unit for testing circuits of semiconductor chips on a semiconductor wafer in the manufacturing process of electronic devices including LSI. More particularly, the present invention relates to an electrical signal connector which includes a probe assembly of a prober apparatus for use in a probing test. In the probing test, circuit terminals (pads) arranged on the semiconductor chips on a wafer are made to contact with vertical probes for collective measurement of electrical conductivity of the semiconductor chips.
2. Description of the Related Art
As the semiconductor technology advances, electronic devices have become more highly integrated and a circuit wiring area has increased in each wafer chip. Pads on each wafer chip have also increased in number, and have become more precisely arranged, whereby pad areas become smaller and pad pitches becomes narrower. The pad pitch will become as narrow as 20 μm in the near future.
Chip size packaging (CSP) becomes dominant in which a bear, non-packaged chip is mounted on a circuit board or other substrate. In fabricating the CSP, characteristics and quality of the chips should be verified at the wafer level.
In an exemplary inspection process, a contact element assembly is disposed between test equipment and pads on semiconductor chips. The contact element assembly includes needle probes each having a section which is elastically deformable due to external force. A printed circuit board called probe card is used for electrically connecting the contact element assembly and test circuits on the semiconductor chips.
The section of the probe card that interfaces with the test head of the test equipment should have compatibility in shape and pitches with those of the test head. At the same time, the section of the probe card near the probes and in contact with the wafer should have compatibility in shape and pitches with those of the chip pad.
A multilayer substrate may be used for converting pitches of closely arranged wirings near the probes into wider pitches of the terminals on the circuit board of the test head.
FIG. 10 shows an example of a conventional probe card which includes a probe card 7 and card substrate 71 to be connected to a test head. A chip 81 to be tested is shown in a perspective view to clarify its positional relationship with the card substrate 71. Terminals 72 arranged at the periphery of the card substrate 71 interface with a test head (not shown) of test equipment. The terminals 72 include sections that have compatibility in shape and pitch with those of the test head.
Probes 91 are attached by a probe alignment fixing device 92 so as to correspond to terminal pads 82 on the chip 81 to be tested on the wafer 8. The probe alignment fixing device 92 can be selected depending on the probe type. A cantilever type probe alignment fixing device 92 may be used for directly soldering the probes 91 to the circuit board. A probe sheet type probe alignment fixing device 92 may include a sheet member such as an electric insulating film having parallel belt-like wirings formed on one side thereof, and a part of the wiring is used as a probe element. An example is shown in Japanese Patent Application Laid-Open No. 2001-183392.
As the chips become more highly-integrated and narrow-pitched, wiring patterns at the periphery of the probe become more and more closely arranged. In order to finally distribute the wiring to peripheral terminals of the card substrate 71, the wiring substrate must be a multi-layer substrate having the wiring arranged densely at the periphery of the probe terminals. In a current practical patterning of a printed circuit board, about 128 to 160 wirings per signal layer is appropriate. For example, a circuit tester with about 1000 pins requires over 20 layers including a power supply layer, having thickness of 4.8 to 6.5 mm, and diameter of about 350 mm.
In terms of economical efficiency of a probe card and a standardized card substrate 71, a conversion wiring board 93 may be disposed between the probe card and the wafer so as to function as a complicated conversion wiring 94 which varies depending on the pad to be tested (See Japanese Patent Application Laid-Open No. 2001-183392).
However, in a conventional electrical signal connector, the wafer may be subject to serious thermal expansion or contraction near the probes due to temperature rise. As a result, the probe contact elements and the chip pads become relatively displaced to cause some probes removed from the pad. In a multilayer substrate for wiring conversion, if the wiring from the probe is firmly connected to the multilayer substrate by means of wiring or pattern wiring, the probe and the connector may disadvantageously be disconnected due to different thermal expansion coefficient in the probe and the wafer. As a result, the wafer cannot be tested any more.
In view of the aforementioned, an object of the invention is to provide an electrical signal connector used for an electrical connection test of semiconductor chips. The electrical signal connector can be used for testing narrow-pitched chips. Even if the invention is used for burn-in testing in which a wafer is placed in a heating device, or if many chips are to be tested simultaneously, occurrence of misalignment between the probes and the pads due to temperature rise can be reduced. Even if misalignment occurs, faulty connection between the probes and the pads or between the probes and the circuit board can be avoided.